Computer systems, or other data processing systems, include integrated circuit devices having a subset of memory in which data is changed more often than data in other subsets of the memory. The subset of memory that is more frequently changed tends to fail to due the effects of the great number of change cycles it undergoes.
A wide variety of endurance enhancement techniques are known to attempt to decrease the potential for failure of the memory cells. For example, redundant memory cells are provided so that if one memory cell fails, another memory cell will take over and provide the required data. Also wear leveling techniques are known in the art.
Most endurance enhancement techniques operate at the block level rather than the bit level. Counters are often used to keep track of the total number of erase/program cycles of a block and then to switch to a redundant block before the first block fails or to occasionally switch blocks to even out the wear.
In U.S. Pat. No. 6,000,006 to Bruce et al., a total-write-counter field indicates a total number of write-erase cycles of the block and an incremental-write-counter field indicates an incremental number of write-erase cycles since a wear-leveling operation for the block. The total and incremental numbers must exceed thresholds for wear leveling for the block change to occur.
Some techniques operate at the bit level. For example, U.S. Pat. No. 4,803,707 to Cordan, Jr. uses an extra memory cell as a backup and writes to both memory cells each time a writing operation is to occur. If one cell fails, the other cell ensures that the data is not lost. However, overall endurance is only marginally improved, since both cells wear at about the same rate.
U.S. Pat. No. 6,157,570 to Nachumovsky reduces wear by avoiding unnecessary erasing of unchanged bits when a new byte is to be written. Since, on average, only one-half of the bits have changes, endurance is doubled. However, a byte write operation is considerably more complicated, because for each bit the existing and new states must first be compared, then a decision made as to whether it needs to be programmed.
It is an object of the present invention to provide a method and system to enhance the endurance of a memory cell or memory cells of an integrated circuit at the bit level.
It is a further object of the present invention to provide a method of managing a sequence of reading and writing data in a storage system.